Thesis Open Access
Eyob Gedlie
<?xml version='1.0' encoding='UTF-8'?> <record xmlns="http://www.loc.gov/MARC21/slim"> <leader>00000nam##2200000uu#4500</leader> <controlfield tag="005">20250110092040.0</controlfield> <controlfield tag="001">5730</controlfield> <datafield tag="856" ind1="4" ind2=" "> <subfield code="s">647925</subfield> <subfield code="z">md5:d45cbd5fd89e1d88df48cadeabb670f7</subfield> <subfield code="u">https://zenodo.org/record/5730/files/f1042664640.pdf</subfield> </datafield> <datafield tag="542" ind1=" " ind2=" "> <subfield code="l">open</subfield> </datafield> <datafield tag="260" ind1=" " ind2=" "> <subfield code="c">2018-12-31</subfield> </datafield> <datafield tag="909" ind1="C" ind2="O"> <subfield code="p">user-aau</subfield> <subfield code="p">user-zenodo</subfield> <subfield code="o">oai:zenodo.org:5730</subfield> </datafield> <datafield tag="100" ind1=" " ind2=" "> <subfield code="a">Eyob Gedlie</subfield> </datafield> <datafield tag="245" ind1=" " ind2=" "> <subfield code="a">Investigation of Soft Neural Network Algorithm Implement to Analog Electronics Devices</subfield> </datafield> <datafield tag="980" ind1=" " ind2=" "> <subfield code="a">user-aau</subfield> </datafield> <datafield tag="980" ind1=" " ind2=" "> <subfield code="a">user-zenodo</subfield> </datafield> <datafield tag="540" ind1=" " ind2=" "> <subfield code="u">http://www.opendefinition.org/licenses/cc-by</subfield> <subfield code="a">Creative Commons Attribution</subfield> </datafield> <datafield tag="650" ind1="1" ind2="7"> <subfield code="a">cc-by</subfield> <subfield code="2">opendefinition.org</subfield> </datafield> <datafield tag="520" ind1=" " ind2=" "> <subfield code="a"><p>The implementation of neural systems is presented in this paper. The thesis focuses on<br> implementations where the algorithms and their physical support are tightly coupled. This thesis<br> describes a neural network intelligent, application, soft-algorithm to implement to hardware<br> electronics device. With the emerging of Integrated Circuit, any design with large number of<br> electronic components can be squeezed into a tiny chip area with minimum power requirements,<br> which leads to integration of innumerable applications so as to design any electronic consumer<br> product initiated in the era of digital convergence. One has many choices for selecting either of<br> these reconfigurable techniques based on Speed, Gate Density, Development, Prototyping,<br> simulation time and cost. This thesis describes the implementation in hardware of an Artificial<br> Neural Network with an Electronic circuit made up of Op-amps. The implementation of a Neural<br> Network in hardware can be desired to benefit from its distributed processing capacity or to avoid<br> using a personal computer attached to each implementation. The hardware implementation is based<br> in a Feed Forward Neural Network, with a hyperbolic tangent as activation function, with floating<br> point notation of single precision. The device used was an electronic circuit made with Op-amps<br> The Proteus Software version 8.0 was used to validate the implementation results of the hardware<br> circuit. The results show that the implementation does not introduce a noticeable loss of precision<br> but is slower than the software implementation running in a PC.</p></subfield> </datafield> <datafield tag="773" ind1=" " ind2=" "> <subfield code="n">doi</subfield> <subfield code="i">isVersionOf</subfield> <subfield code="a">10.20372/nadre:5729</subfield> </datafield> <datafield tag="024" ind1=" " ind2=" "> <subfield code="a">10.20372/nadre:5730</subfield> <subfield code="2">doi</subfield> </datafield> <datafield tag="980" ind1=" " ind2=" "> <subfield code="a">publication</subfield> <subfield code="b">thesis</subfield> </datafield> </record>
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