Thesis Open Access
Eyob Gedlie
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<foaf:name>Eyob Gedlie</foaf:name>
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<dct:title>Investigation of Soft Neural Network Algorithm Implement to Analog Electronics Devices</dct:title>
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<dct:issued rdf:datatype="http://www.w3.org/2001/XMLSchema#gYear">2018</dct:issued>
<dct:issued rdf:datatype="http://www.w3.org/2001/XMLSchema#date">2018-12-31</dct:issued>
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<dct:description><p>The implementation of neural systems is presented in this paper. The thesis focuses on<br> implementations where the algorithms and their physical support are tightly coupled. This thesis<br> describes a neural network intelligent, application, soft-algorithm to implement to hardware<br> electronics device. With the emerging of Integrated Circuit, any design with large number of<br> electronic components can be squeezed into a tiny chip area with minimum power requirements,<br> which leads to integration of innumerable applications so as to design any electronic consumer<br> product initiated in the era of digital convergence. One has many choices for selecting either of<br> these reconfigurable techniques based on Speed, Gate Density, Development, Prototyping,<br> simulation time and cost. This thesis describes the implementation in hardware of an Artificial<br> Neural Network with an Electronic circuit made up of Op-amps. The implementation of a Neural<br> Network in hardware can be desired to benefit from its distributed processing capacity or to avoid<br> using a personal computer attached to each implementation. The hardware implementation is based<br> in a Feed Forward Neural Network, with a hyperbolic tangent as activation function, with floating<br> point notation of single precision. The device used was an electronic circuit made with Op-amps<br> The Proteus Software version 8.0 was used to validate the implementation results of the hardware<br> circuit. The results show that the implementation does not introduce a noticeable loss of precision<br> but is slower than the software implementation running in a PC.</p></dct:description>
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