December 31, 2018 Thesis Open Access

Eyob Gedlie

DataCite XML Export

<?xml version='1.0' encoding='utf-8'?>
<resource xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://datacite.org/schema/kernel-4" xsi:schemaLocation="http://datacite.org/schema/kernel-4 http://schema.datacite.org/meta/kernel-4.1/metadata.xsd">
  <identifier identifierType="DOI">10.20372/nadre:5730</identifier>
  <creators>
    <creator>
      <creatorName>Eyob Gedlie</creatorName>
    </creator>
  </creators>
  <titles>
    <title>Investigation of Soft Neural Network Algorithm Implement to Analog Electronics Devices</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2018</publicationYear>
  <dates>
    <date dateType="Issued">2018-12-31</date>
  </dates>
  <resourceType resourceTypeGeneral="Text">Thesis</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://nadre.ethernet.edu.et/record/5730</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsVersionOf">10.20372/nadre:5729</relatedIdentifier>
    <relatedIdentifier relatedIdentifierType="URL" relationType="IsPartOf">https://nadre.ethernet.edu.et/communities/aau</relatedIdentifier>
    <relatedIdentifier relatedIdentifierType="URL" relationType="IsPartOf">https://nadre.ethernet.edu.et/communities/zenodo</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="http://www.opendefinition.org/licenses/cc-by">Creative Commons Attribution</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;The implementation of neural systems is presented in this paper. The thesis focuses on&lt;br&gt;
implementations where the algorithms and their physical support are tightly coupled. This thesis&lt;br&gt;
describes a neural network intelligent, application, soft-algorithm to implement to hardware&lt;br&gt;
electronics device. With the emerging of Integrated Circuit, any design with large number of&lt;br&gt;
electronic components can be squeezed into a tiny chip area with minimum power requirements,&lt;br&gt;
which leads to integration of innumerable applications so as to design any electronic consumer&lt;br&gt;
product initiated in the era of digital convergence. One has many choices for selecting either of&lt;br&gt;
these reconfigurable techniques based on Speed, Gate Density, Development, Prototyping,&lt;br&gt;
simulation time and cost. This thesis describes the implementation in hardware of an Artificial&lt;br&gt;
Neural Network with an Electronic circuit made up of Op-amps. The implementation of a Neural&lt;br&gt;
Network in hardware can be desired to benefit from its distributed processing capacity or to avoid&lt;br&gt;
using a personal computer attached to each implementation. The hardware implementation is based&lt;br&gt;
in a Feed Forward Neural Network, with a hyperbolic tangent as activation function, with floating&lt;br&gt;
point notation of single precision. The device used was an electronic circuit made with Op-amps&lt;br&gt;
The Proteus Software version 8.0 was used to validate the implementation results of the hardware&lt;br&gt;
circuit. The results show that the implementation does not introduce a noticeable loss of precision&lt;br&gt;
but is slower than the software implementation running in a PC.&lt;/p&gt;</description>
  </descriptions>
</resource>