Thesis Open Access
Eyob Gedlie
{
"files": [
{
"links": {
"self": "https://nadre.ethernet.edu.et/api/files/73003108-1238-4950-882f-f9b41373f8cd/f1042664640.pdf"
},
"checksum": "md5:d45cbd5fd89e1d88df48cadeabb670f7",
"bucket": "73003108-1238-4950-882f-f9b41373f8cd",
"key": "f1042664640.pdf",
"type": "pdf",
"size": 647925
}
],
"owners": [
11
],
"doi": "10.20372/nadre:5730",
"stats": {},
"links": {
"doi": "https://doi.org/10.20372/nadre:5730",
"conceptdoi": "https://doi.org/10.20372/nadre:5729",
"bucket": "https://nadre.ethernet.edu.et/api/files/73003108-1238-4950-882f-f9b41373f8cd",
"conceptbadge": "https://nadre.ethernet.edu.et/badge/doi/10.20372/nadre%3A5729.svg",
"html": "https://nadre.ethernet.edu.et/record/5730",
"latest_html": "https://nadre.ethernet.edu.et/record/5730",
"badge": "https://nadre.ethernet.edu.et/badge/doi/10.20372/nadre%3A5730.svg",
"latest": "https://nadre.ethernet.edu.et/api/records/5730"
},
"conceptdoi": "10.20372/nadre:5729",
"created": "2025-01-10T09:20:36.329091+00:00",
"updated": "2025-01-10T09:20:40.536090+00:00",
"conceptrecid": "5729",
"revision": 3,
"id": 5730,
"metadata": {
"access_right_category": "success",
"doi": "10.20372/nadre:5730",
"description": "<p>The implementation of neural systems is presented in this paper. The thesis focuses on<br>\nimplementations where the algorithms and their physical support are tightly coupled. This thesis<br>\ndescribes a neural network intelligent, application, soft-algorithm to implement to hardware<br>\nelectronics device. With the emerging of Integrated Circuit, any design with large number of<br>\nelectronic components can be squeezed into a tiny chip area with minimum power requirements,<br>\nwhich leads to integration of innumerable applications so as to design any electronic consumer<br>\nproduct initiated in the era of digital convergence. One has many choices for selecting either of<br>\nthese reconfigurable techniques based on Speed, Gate Density, Development, Prototyping,<br>\nsimulation time and cost. This thesis describes the implementation in hardware of an Artificial<br>\nNeural Network with an Electronic circuit made up of Op-amps. The implementation of a Neural<br>\nNetwork in hardware can be desired to benefit from its distributed processing capacity or to avoid<br>\nusing a personal computer attached to each implementation. The hardware implementation is based<br>\nin a Feed Forward Neural Network, with a hyperbolic tangent as activation function, with floating<br>\npoint notation of single precision. The device used was an electronic circuit made with Op-amps<br>\nThe Proteus Software version 8.0 was used to validate the implementation results of the hardware<br>\ncircuit. The results show that the implementation does not introduce a noticeable loss of precision<br>\nbut is slower than the software implementation running in a PC.</p>",
"license": {
"id": "cc-by"
},
"title": "Investigation of Soft Neural Network Algorithm Implement to Analog Electronics Devices",
"relations": {
"version": [
{
"count": 1,
"index": 0,
"parent": {
"pid_type": "recid",
"pid_value": "5729"
},
"is_last": true,
"last_child": {
"pid_type": "recid",
"pid_value": "5730"
}
}
]
},
"communities": [
{
"id": "aau"
},
{
"id": "zenodo"
}
],
"publication_date": "2018-12-31",
"creators": [
{
"name": "Eyob Gedlie"
}
],
"access_right": "open",
"resource_type": {
"subtype": "thesis",
"type": "publication",
"title": "Thesis"
},
"related_identifiers": [
{
"scheme": "doi",
"identifier": "10.20372/nadre:5729",
"relation": "isVersionOf"
}
]
}
}
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